1. Field of the Invention
The present invention is directed in general to communications systems and methods for operating same, and more particularly to efficient implementation of a hash algorithm on a processor.
2. Description of the Related Art
In known wireless telecommunications systems, transmission equipment in a base station or access device transmits signals throughout a geographical region known as a cell. As technology has evolved, more advanced equipment has been introduced that can provide services that were not possible previously. This advanced equipment might include, for example, an E-UTRAN (evolved universal terrestrial radio access network) node B (eNB), a base station or other systems and devices. Such advanced or next generation equipment is often referred to as long-term evolution (LTE) equipment, and a packet-based network that uses such equipment is often referred to as an evolved packet system (EPS). An access device is any component, such as a traditional base station or an LTE eNB (Evolved Node B), that can provide a communication device, such as user equipment (UE) or mobile equipment (ME), with access to other components in a telecommunications system.
One issue that is present in many UE type devices relates to providing security such as via a hash algorithm. SHA-512 is a Hash algorithm from the second generation secure hash algorithm (SHA-2) family (see e.g., the FIPS180-3 hashing standard). It includes 80 rounds of repeated operations on a state consisting of eight 64-bit words. The implementation of SHA-512 on an advanced reduced instruction set computer (risc) machine type ARM processor, such as the ARMv5t architecture, is a challenging task since it comprises sixteen 32-bit registers of which one is the program counter (PC) and the other is the stack pointer (SP). Hence, the SHA-512 state cannot be entirely kept in the 14 working registers, only portions of it at a time would be loaded into them and undergo the necessary calculations before being stored back on the stack. The challenge lies in optimizing the registers utilization and minimizing the relatively lengthy load operations.